1. Field of the Invention
The present invention relates to integrated circuits, and, in particular, to programmable gate arrays and application-specific integrated circuits.
2. Description of the Related Art
Programmable gate arrays constitute one family of integrated circuits. There are different types of programmable gate arrays. A mask-programmable gate array (MPGA) (also known as a factory-programmable gate array) is a type of mask-programmed integrated circuit that is programmed one time and typically by the manufacturer of the gate array. Other types of mask-programmed devices (MPDs) include full-custom devices and standard-cell devices. A field-programmable gate array (FPGA), on the other hand, is a type of gate-array integrated circuit that can be programmed by the user. An FPGA can be one-time programmable or re-programmable, in which case the user can re-program the gate array one or more times.
FIG. 1 shows a schematic diagram of a conventional FPGA 100, having an array 102 of programmable logic cells (PLCs) surrounded by a ring 104 of programmable input/output (I/O) cells (PICs) and an outermost ring 106 of pads. The PLCs and PICs can be programmed (and possibly reprogrammed) in the field to implement a desired set of functions. This programming is typically done through the configuration interface of the FPGA, which reads a stream of bits and writes to the internal configuration storage (SRAM, EEPROM, anti-fuse, etc.), which in turn controls the programmable logic and routing. The PICs operate as the interfaces between the array of PLCs and individual pads, which provide connections to the "outside world," that is, circuitry external to the FPGA. Programmable general routing resources (not shown in FIG. 1) are used to implement specific connections between PLC array 102 and PIC ring 104 (i.e., PLC-PIC connections) as well as specific connections within PLC array 102 (i.e., PLC-PLC connections) and within PIC ring 104 (i.e., PIC-PIC connections).
FIG. 2 shows a detail of a portion of FPGA 100 of FIG. 1. According to one conventional design, each PIC in ring 104 is associated with four pads and has four corresponding sets of pad logic. FIG. 2 shows a schematic diagram of the circuitry of FPGA 100 that is associated with one of these sets of pad logic. PLC logic 202 and PLC local routing 204 are part of PLC array 102 of FIG. 1. Similarly, PIC local routing 208 and PIC logic 210 are part of PIC ring 104 of FIG. 1, while pad 212 is one of the pads of pad ring 106 of FIG. 1. General routing resources 206 correspond to the programmable routing and logic used to connect individual sets of PLC logic to individual sets of PIC logic. PIC logic 210 comprises an output buffer 216 and an input buffer 218, as well as boundary scan and other miscellaneous PIC logic 214, such as optional flip-flops and latches.
FIG. 3 shows a schematic diagram of one of the three main types of mask-programmed devices--a conventional MPGA 300, having an array of gates 302 surrounded by a ring of pads 306. Typically, the array of gates and the ring of pads are interconnected with each other by conductive (typically metal) wires to implement a desired set of functions. The ring of pads serves the same purpose of interfacing to the "outside world" as the ring of pads in FPGA 100 of FIG. 1. In a typical MPGA, the array of gates and the array of pads are pre-defined and the user can only define how they are interconnected at the factory. The other two main types of MPDs are standard-cell devices, which have rows of standard cells instead of an array of gates, and full-custom devices, which have individual transistors instead of an array of gates. These two types of devices also differ from MPGAs in that the rows of standard cells and the arrays of transistors are not pre-fixed, thus allowing increased functionality.
An FPGA, such as FPGA 100 of FIG. 1, has the flexibility to implement many different logic functions using the same silicon, although the cost of this flexibility is in chip layout area, performance (i.e., speed and power dissipation), and dollar cost. An MPGA could be designed to implement the same piece of logic with less area and optimal performance, translating into a lower dollar cost. The cost of using an MPGA, however, is that, once it is manufactured, the logic function cannot be changed by the user.
The present invention is directed to a scheme for exploiting both the programming flexibility advantages of FPGAs and the size, speed, functionality, and dollar cost advantages of MPDs.